TMP401
SBOS371A AUGUST 2006 REVISED OCTOBER 2007
www.ti.com
17
Frame 1 TwoWire Slave Address Byte
Frame 2 Pointer Register Byte
1
Start By
Master
ACK By
TMP401
ACK By
TMP401
Frame 3 TwoWire Slave Address Byte
Frame 4 Data Byte 1 Read Register
Start By
Master
ACK By
TMP401
ACK By
Master
From
TMP401
1
9
1
9
1
9
1
9
SDA
SCL
0
0
1
R/W
P7 P6 P5 P4 P3 P2 P1 P0
&
&
&
&
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
1
0
0
1
1
0
0
1
0
0
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Frame 5 Data Byte 2 Read Register
Stop By
Master
ACK By
Master
From
TMP401
1
9
D7 D6 D5 D4 D3 D2 D1 D0
Figure 15. Two-Wire Timing Diagram for Read Word Format
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address Byte
Start By
Master
ACK By
TMP401
From
TMP401
NACK By
Master
Stop By
Master
1
9
1
9
SDA
SCL
ALERT
0
0
0
1
1
0
0 R/W
1
0
0
1
1
0
0
Status
Figure 16. Timing Diagram for SMBus ALERT
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